Chip designers are under constant pressure to enhance performance of chips while simultaneously minimizing cost. One way to achieve this is by speeding up the verification process – as verification constitutes more than 70% of the entire chip design process, embracing tools and technologies that result in faster verification is the need of the hour.
The Need for Hardware Assisted Verification Models
In order to meet the demands of shortened development cycles, it is essential for hardware and software on a chip to be verified at the same time. Since software development cannot wait till the hardware aspects of the chip are developed, design teams need to adopt a fail-safe way to verify chips will work as intended as soon as the embedded software is run. This requires the design team to create a working prototype for software development as early as possible, and much before the end of the hardware design cycle.
Hardware Assisted Technology
Given time-to-market pressures, the process of verification has come a long way. For many digital design engineers, there are some compelling reasons for performing hardware-assisted verification. Since performance is key, it is important for verification systems to deliver the highest performance models and environment for SoC verification.
• Hardware acceleration techniques help overcome the challenge of meeting the performance requirements for SoC verification.
• Writing SystemVerilog testbenches for a specific piece of design can be very laborious, especially while testing the interaction between different blocks.
• With hardware-assisted verification, you do not have to write the testbench or worry about how the interfaces will be exercised.
• For example, to check if a peripheral device works as intended, you can take a physical or virtual peripheral device, connect it up to the design and then use the device driver for the controller to perform functions to see if the interface works.
• As the number of vectors that can be run per second is substantial, you can make sure that the interaction between hardware and software is as expected in shorten span of time
• Hardware accelerators allow you to use components like FPGAs to build the hardware platform.
• Using embedded test benches, you can perform hardware-assisted verification and virtualize the environment to speed up the verification process.
With increases in the size and complexity of today’s SoC devices, verification requires you to conduct massive tests spanning billions of cycles. Using advanced verification technologies like hardware-assisted emulation systems, you can accelerate the verification process and deliver the highest performance possible:
• Modern emulation systems encompass a broad portfolio of transactors and memory models that speed up the development of virtual system level verification environments.
• Emulation systems offer comprehensive debug with full signal visibility and support advanced use modes including power management verification and hybrid emulation
• With emulation, the design-under-test (DUT) is usually represented in the emulator, while the chip’s environment can be provided by connections outside the emulator.
• By using virtual bridges in conjunction with virtual test environments, you can connect the DUT through protocol-specific transactors to real devices
• In addition, system-level debug components can also be used to understand the high-level behaviour of SoCs.
Another way to improve the verification process is to use physical prototyping to meet time-to-market requirements.
• By leveraging a hardware assisted system environment, prototyping enables early embedded software development, allowing hardware and software to co-exist well ahead of chip fabrication.
• You can shorten design schedules and avoid costly device re-spins through the use of tightly integrated and easy-to-use hardware and tools, and accelerate the process of software development
• Hardware-assisted prototyping enables you to eliminate redundant IP prototyping tasks by using pre-tested components and maximize ROI by applying modular systems across multiple projects
• You can make your products immediately available using the latest generation of FPGA devices, bypassing the effort and expense of custom-built systems
Reduce Verification Effort
Although as a designer, you may choose different methods for verification, the fact remains that hardware-assisted technology can help you speed the overall verification effort. Hardware-assisted verification reduces the amount of effort – in developing the model as well as in writing the test benches. You not only speed up the verification of the hardware, but also quicken the process of debugging, and ensure faster time-to-market.
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